Related fields include semiconductor devices and their fabrication; in particular, thin-film components included in individual cells of non-volatile memory based on resistive switching (ReRAM).
Nonvolatile memory elements are used in computers and other devices requiring persistent data storage (e.g., cameras, music players). Some traditional nonvolatile memory technologies (e.g., EEPROM, NAND flash) have proven difficult to scale down to smaller or higher-density configurations. Therefore, a need has developed for alternative nonvolatile memory technologies that can be scaled down successfully in terms of performance, reliability, and cost.
In resistive-switching-based nonvolatile memory, each individual cell includes a resistor that is bistable; it can be put into either of two states (low-resistance or high-resistance), and will stay in that state until receiving the type of input that changes it to the other state. The state of the bistable memory cell represents a bit value (e.g., the low-resistance state may represent “1” and the high-resistance state may represent “0”). The cell is thus “written” to by changing its resistance value. The cell is “read” by measuring its resistance in a way that does not change it. Ideally, write and read operations should require as little power as possible, both to conserve energy and to avoid generating unwanted heat.
FIG. 1A is a perspective view of an example memory array. Such a memory array may be part of a larger device, such as a system-on-a-chip. Multiple memory arrays may be stacked in a vertical fashion to make multilayer memory array structures. The memory array includes multiple ReRAM cells 100. Each cell 100 includes a switching stack 112 formed from multiple thin-film material layers 114. Material layers 114 typically include one or more bistable variable resistance (VR) layers between two or more electrode layers. Electrical signals flow from one electrode to the other through the VR layer(s) to read or write the cell.
Connections 102 and connections 118, sometimes called “bit-lines” and “word-lines” respectively, interconnect the cells in the array and connect the array to other circuit elements, such as power sources and read/write circuitry (not shown). In some arrays, connections 102 and connections 118 serve as the electrodes for the ReRAM cells; in others, the connections are connected to separately-formed electrodes in the material layers of each cell 100.
FIG. 1B is a simplified electrical schematic of the example memory array showing the ReRAM cells 100 connected by bit-lines 102 and word-lines 118. Each cell 100 can be read or written individually through the word-line 118 and bit line 102 that intersect at that particular cell 100. In some memory arrays, a ReRAM cell 100 may include a current-steering element 116 (e.g., a diode, or some other element that similarly constrains a direction of current flow) connected in series with switching stack. Current-steering element 116 constrains current to flow through only those ReRAM cells 100 for which the intersecting word-lines 118 and bit-lines 102 are selected. The current-steering elements, if present, are also fabricated from thin films and are included in material layers 114 in FIG. 1A.
FIG. 1C is an example “I-V curve” of measured current I (on a logarithmic scale) plotted against applied voltage V for ReRAM cell 100. The bistable VR layer(s) in switching stack 112 may be placed either of two stable states: a low-resistance state (R=RL) or a high-resistance state (R=RH). Each state yields a different I-V curve: curve 120 is produced when R=RL and curve 124 is produced when R=RH.
A write operation may either “set” (126) the resistance of switching stack 112 from its high state to its low state or “reset” (128) the resistance from its low state to its high state. A “set” switching pulse of voltage Vset applied to ReRAM cell 100 induces a high-to-low resistance transition, which in turn causes the current flowing through the cell to drop from I(Vset,RH) to I(Vset,RL), following arrow 126 on the graph. Similarly, a “reset” switching pulse of voltage Vreset applied to ReRAM cell 100 induces a low-to-high resistance transition, which in turn causes the current flowing through the cell to drop from I(Vreset,RL) to I(Vreset,RH), following arrow 128. This example uses bipolar switching; the set and reset pulses are of opposite polarity. Some ReRAM designs use unipolar switching, with set and reset pulses of the same polarity.
To read the resistance state of ReRAM cell 100, a voltage pulse may be applied and the resulting current (which depends on the cell's resistance state) may be measured. A read operation senses the resistance state of ReRAM cell 100 without changing it. Accordingly, the magnitude Vread of a read pulse is significantly smaller than the write voltages Vset and Vreset (e.g., a read pulse may only be ⅛-⅓ of the voltage of a write pulse). When a Vread pulse is applied to ReRAM cell 100, the measured current will either be I(Vread,RH) or I(Vread,RL) depending on the cell's resistance state. If the logic value “0” is assigned to the high-resistance state and the logic value “1” is assigned to the low-resistance state, then a response of I(Vread,RH) to a Vread pulse will be interpreted as a stored “0” and a response of I(Vread, RL) will be interpreted as a stored “1.” In this example, Vread is positive, but a negative Vread of sufficiently small magnitude could alternatively be used.
According to working hypotheses that seem to fit empirical data so far, in at least some types of ReRAM the resistance change in the VR layer of a cell is not homogeneous throughout the layer. In the low-resistance state, charge carriers (e.g., oxygen or nitrogen vacancies) in the VR layer(s) are assembled into a “filament” traversing the entire VR layer. The filament provides a localized lower-resistance path for current. In the high-resistance state, the filament is incomplete or absent. This means that the set pulse must create or assemble the filament and the reset pulse must break, disperse, or destroy it.
To predispose the VR layer to create a filament, a “forming voltage” pulse, with a magnitude much larger than a set or reset pulse, may be applied to newly fabricated ReRAM cells. The forming pulse creates defects (e.g., oxygen vacancies) in the VR layer(s) or at the interface of a VR layer and an electrode made of an oxidizable material (a “source electrode” acting as a cathode), and drives them through the stack to the other electrode (often made of a noble or inert material) that acts as an anode.
FIGS. 2A-2F conceptually illustrate filament behavior in a simple ReRAM switching stack with a single metal-oxide (“MeOx”) VR layer. In FIG. 2A, the stack of source electrode 201, VR layer 202, and inert electrode 203 has just been fabricated. VR 202 is typically crystalline; many of the high-k transition-metal oxides (e.g. HfOx, TiOx) crystallize after the annealing steps required to fabricate other layers (e.g., the 750 C anneal required in the fabrication of some current-steering elements). At this point, the as-fabricated resistance R0 of VR layer 202 is at least as high as its operating high-resistance state RH will be; in many cases, higher.
In FIG. 2B, forming voltage 210 has just been applied between electrodes 201 and 203. Source electrode 201 acts as the cathode; oxygen vacancies 211 begin to develop where source electrode 201 meets VR layer 202. The reaction near that interface may be, for example, MeO2+2xe−→MeO2-x+xO2−. Inert electrode 203 acts as the anode; the reaction near that interface may be, for example, 2O2−→O2+4e−.
In FIG. 2C, the forming operation is being completed and forming voltage pulse 210 is about to end. More oxygen vacancies 211 have been created and/or pushed through the VR layer, constituted into filament 212C—a chain of charge-carriers reaching from the vicinity of source electrode 201 to the vicinity of inert electrode 203. Filament 212C is a path of least resistance for current flowing from source electrode 201 to inert electrode 203; electrons may “hop” between vacancies that are sufficiently close to each other. Electron diffraction and other measurements have revealed room-temperature-conductive Magneli phase compounds localized in some filaments. The presence of complete filament 212C changes the effective resistance of VR layer 202 to its low-resistance state RL. Tunneling electron microscopy (TEM) and other techniques have revealed that partial filaments 213 may also develop during the forming operation.
In FIG. 2D, a reset pulse 220D has been applied to the stack. The illustrated example uses bipolar switching; the reset pulse has a polarity opposite that of the forming pulse and set pulse, so that inert electrode 203 becomes the cathode and source electrode 201 becomes the anode. Because inert electrode 203 does not oxidize easily, the reset pulse did not create more vacancies 211, but instead destroyed or dispersed those vacancies 211 nearest to inert electrode 203. It is believed that filament destruction by the reset pulse in bipolar-switching ReRAM results from a heat-assisted electrochemical reaction. Filament 212C was narrowest at the tip near inert electrode 203; perhaps 3 nm wide or less. A few microamps, when concentrated in such a small area, can create a current density on the order of 107-108 A/cm2. This is a very intense field that can dissipate a great deal of heat.
Filament 212C is not completely destroyed, however. Instead it has been reduced to a partial filament, somewhat similar to partial filament 213. Electrons can now only hop between vacancies as far as filament break-point 214D. The remaining path between break-point 214D and inert electrode 203 is through substantially vacancy-free, and therefore less conductive, VR material with a local R˜R0. The high-resistance state RH of the VR layer depends in part on both R0 and the depth of break-point 214D.
In FIG. 2E, a set pulse 230 has been applied. Set pulse 230 has the same polarity as forming pulse 210, causing source electrode 201 to again function as the cathode. As a result, more vacancies 211 are created and pushed through VR layer 202 until they constitute another filament 212E. Because current can now flow through a completed filament 212E, the VR layer has returned to a low-resistance state RL. Note that set pulse 230 did not need to form filament 212E through the entire thickness of VR layer 202; it only needed to bridge the thinner gap between break-point 214D and inert electrode 203.
In FIG. 2F, a subsequent reset pulse 220F has been applied to the stack. Filament 214D has been reduced to a partial filament with break-point 214F. Ideally, break-point 214F would be at the same location as break-point 214D, but in practice it is often different. This means that each set pulse may have to bridge a gap of a different size to create a filament. There may be some circumstances where a new filament originates from a different place, such as terminus 215 of pre-existing partial filament 213. These break-point variations occur not only from write-cycle to write-cycle in a single ReRAM cell, but from cell to cell in a memory array.
In addition, variation in the location of the filament break-point from cycle to cycle causes a corresponding variation in RL and RH. This in turn causes a variation in I(Vread,RL) and I(Vread,RH). Too much variation in each of these currents, when added to tolerances in the rest of the device, may result in mistaken readings (e.g., a “0” is read from a cell where a “1” is stored). Referring back to FIG. 1C, the probability of a mistaken reading can be reduced by increasing the magnitude of Vread, because the curves diverge with increasing magnitude of voltage. However, this means that operation consumes more power, which is undesirable.
Therefore, a need exists for a ReRAM design in which the filament break-point is controllable, predictable, repeatable from cycle to cycle in a single ReRAM cell, and consistent between ReRAM cells in a memory array and from array to array in production. A need also exists for a ReRAM design that can operate with reduced power consumption compared to the current state of the art.